1. Field of the Invention
The present invention relates to a semiconductor device having a solid device (a semiconductor chip or a wiring board) and a semiconductor chip bonded thereto. The invention further relates to a semiconductor chip to be bonded to a solid device.
2. Description of Related Art
For substantial increase in integration level, attention has been directed to semiconductor devices of chip-on-chip structure in which a plurality of semiconductor chips are arranged in a double-stacked relation.
In this case, electrode projections called xe2x80x9cbumpsxe2x80x9d are provided on a device formation surface (active surface) of the semiconductor chips to be stacked, and the semiconductor chips are stacked in a so-called face-to-face relation.
However, the face-to-face bonding merely realizes a double-stacked structure but not a multi-level structure comprising semiconductor chips stacked at three or more levels, thereby posing limitations to higher density integration.
Where a semiconductor chip is mounted by a so-called face-up bonding method to form the chip-on-chip structure, wire interconnection is required for connecting electrodes on a device formation surface of the semiconductor chip to electrodes on an underlying substrate.
More specifically, the TAB (tape automated bonding) technique is employed, by which the electrodes on the device formation surface of the base semiconductor chip are connected to the electrodes of the underlying substrate (e.g., wiring board) via inner leads and the electrodes on the underlying substrate are connected to a printed board or a ceramic board.
The underlying substrate is indispensable for such wire interconnection, so that the underlying substrate cannot be obviated. Further, higher density integration is impossible with a need for an underlying substrate having a larger plan area.
It is an object of the present invention to provide a semiconductor chip which can be bonded to a solid device (another semiconductor chip or a wiring substrate) with an increased flexibility, thereby realizing higher integration and higher density packaging.
It is another object of the invention to provide a semiconductor device which features an increased flexibility in bonding between a semiconductor chip and a solid device (another semiconductor chip or a wiring board), thereby realizing higher integration and higher density packaging.
A more specific object of the invention is to arrange semiconductor chips in any stacked relation to form a chip-on-chip structure, thereby easily realizing a semiconductor device of multi-level structure comprising semiconductor chips stacked at three or more levels.
Another specific object of the invention is to provide a semiconductor device including a semiconductor chip which can be connected directly to a printed board or the like without the use of an underlying substrate when the semiconductor chip is packaged with its device formation surface facing upward (in a face-up manner).
The semiconductor device according to the present invention comprises a solid device, and a semiconductor chip bonded to the solid device with a back face thereof being opposed to a front face of the solid device, the semiconductor chip having a back electrode provided on the back face thereof and electrically connected to an electrode provided on a front face thereof through a through-hole. The back electrode is bonded, for example, to a connecting portion provided on the front face of the solid device.
The solid device may be another semiconductor chip.
Further another semiconductor chip may be stacked and bonded onto the front face of the semiconductor chip.
The solid device may be a wiring board. In this case, the back electrode is preferably bonded to a lead of the wiring board.
The semiconductor chip according to the present invention comprises a semiconductor substrate formed with a through-hole, a front electrode provided on a front face of the semiconductor substrate as a device formation surface thereof, and a back electrode provided on a back face of the semiconductor substrate and electrically connected to the front electrode through the through-hole.
In accordance with the invention, the back electrode is connected to the front electrode through the through-hole, so that a plurality of semiconductor chips can be connected to each other in any stacked relation such as a face-to-back, face-to-face or back-to-back relation. Thus, a semiconductor device can be realized which has a chip-on-chip structure comprising semiconductor chips stacked at any number of levels, i.e., two levels and three or more levels.
Even where the semiconductor chip is packaged with the device formation surface thereof facing upward (in a face-up manner), electrode connection can be established with the use of the back electrode provided on the back face of the chip, so that the semiconductor chip can be connected directly to a printed board or the like. Further, higher density packaging can be achieved because provision of an underlying substrate is obviated.
The back electrode is preferably connected to the front electrode via a through-interconnection provided in the through-hole.
A front interconnection may be provided on the front face of the semiconductor substrate for connection between the through-interconnection and the front electrode.
A back interconnection may be provided on the back face of the semiconductor substrate for connection between the through-interconnection and the back electrode.
The front electrode may comprise a bump projecting from the front face of the semiconductor substrate. In this case, the back electrode, the through-interconnection, the front interconnection or the back interconnection is preferably composed of the same material as the bump.
Thus, the through-interconnection extending through the through-hole can easily be formed by plating or the like for bump formation. Further, electrical connection between vertically stacked semiconductor chips can be established by bump bonding. In addition, stresses exerted on the semiconductor chips can be absorbed by the bumps.
The bump material generally has properties suitable for the electrodes, i.e., a lower electrical resistance and a higher heat conductivity.
In addition, the back electrode, the through-interconnection, the front interconnection or the back interconnection can be formed simultaneously with the formation of the bump. In this case, the formation of any of these elements can be achieved without employing any other steps for element formation.
Of course, the back electrode, the through-interconnection, the front interconnection or the back interconnection may be formed in a later step after the formation of the bump on a pad electrode.
Where the front interconnection is composed of the same material as the bump, the bump can be used in place of a part of chip internal interconnection, so that further integration can be achieved.
The bump preferably has a greater height than the front interconnection.
The front or back face of the semiconductor substrate or the interior of the through-hole is preferably covered with an insulating film. The back electrode, the through-interconnection, the front electrode, the front interconnection or the back interconnection is preferably provided on the insulating film. Thus, a plurality of electrodes can electrically be isolated from each other. Particularly, where a semiconductor substrate such as of Ge or Si having a high electrical conductivity is employed, the insulation is required.
The front electrode may comprise an electrode pad which is a portion of an internal interconnection exposed from the insulating film provided on the front face of the semiconductor substrate.
The through-hole is preferably provided adjacent the electrode pad.
The bump is preferably provided on the electrode pad as covering the electrode pad.
The through-hole is provided just below the electrode pad. With this arrangement, the amount of the material (bump material) for the through-interconnection disposed in the through-hole can be minimized because the electrode pad and the through-hole are located in the same position as viewed in plan. This allows for resource saving and minimization of electrical resistance.
The foregoing and other objects, features and effects of the present invention will become more apparent from the following description of the preferred embodiments with reference to the attached drawings.